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www.latticesemi.com 4-1 ds1011_01.6 february 2009 data sheet ds1011 ?2009 lattice semiconductor corp. all lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www .latticesemi.com/legal. all other brand or product names are trademarks or registered trademarks of their respective holders. the speci?ations and information h erein are subject to change without notice. features power-down mode i cc < 10? programmable threshold monitors simultaneously monitors up to six power supplies programmable analog trip points (1% step size; 192 steps) programmable glitch ?ter power-off detection (75mv) embedded programmable timers four independent timers 32? to 2 second intervals for timing sequences embedded pld for logical control rugged 16-macrocell cpld architecture 81 product terms / 28 inputs implements state machines and combinatorial functions digital i/o two dedicated digital inputs five programmable digital i/o pins two high-voltage fet drivers power supply ramp up/down control independently con?urable for fet control or digital output wide supply range (2.64v to 3.96v) in-system programmable through jtag industrial temperature range: -40? to +85? 32-pin qfns (q uad f lat-pack, n o lead, s aw- singulated) package, lead-free option 1 description lattices power manager ii ISPPAC-POWR607 is a gen- eral-purpose power-supply monitor, reset generator and watchdog timer, incorporating both in-system program- mable logic and analog functions implemented in non- volatile e 2 cmos technology. the ISPPAC-POWR607 device provides six independent analog input channels to monitor power supply voltages. two general-purpose digital inputs are also provided for miscellaneous control functions. the ISPPAC-POWR607 provides up to seven open-drain digital outputs that can be used for controlling dc-dc 1. use 32-pin qfns package for all new designs. refer to pcn #13a-08 for 32-pin qfn package discontinuance. converters, low-drop-out regulators (ldos) and opto- couplers, as well as for supervisory and general-pur- pose logic interface functions. two of these outputs (hvout1-hvout2) can be con?ured as high-voltage mosfet drivers. in high-voltage mode these outputs provide 9v for driving the gates of n-channel mosfets used as high-side power switches to control power sup- ply ramp up and ramp down rate. the remaining ?e digital, open drain outputs can optionally be con?ured as digital inputs to sense more input signals as needed, such as manual reset, etc. the diagram above shows how a ISPPAC-POWR607 is used in a typical application. it controls power to the microprocessor system, generates the cpu reset and monitors critical power supply voltages, generating interrupts whenever faults are detected. it also provides a watchdog timer function to detect cpu operating and bus timeout errors. the ISPPAC-POWR607 incorporates a 16-macrocell cpld. figure 4-1 shows the analog input comparators application block diagram v oltage s u per v isor ISPPAC-POWR607 reset generator w atchdog timer po w er do w n dc-dc #1 dc-dc #2 dc-dc #n mosfet dri v ers (2) inp u t po w er s u pply on/off po w er up/do w n control power supply bus cpu / uprocessor interr u pt po w er fail cpu_reset_in w dt trigger interr u pt ? w dt man u al reset in ISPPAC-POWR607 in-system programmable power supply supervisor, reset generator and watchdog timer www.datasheet.co.kr datasheet pdf - http://www..net/
lattice semiconductor ISPPAC-POWR607 data sheet 4-2 and digital inputs used as inputs to the cpld array. the digital output pins providing the external control signals are driven by the cpld. four independently programmable timers also interface with the cpld and can create delays and time-outs ranging from 32? to 2 seconds. the cpld is programmed using logibuilder, an easy-to-learn language integrated into the pac-designer software. control sequences are written to monitor the status of any of the analog input channel comparators or the digital inputs. figure 4-1. ISPPAC-POWR607 block diagram pin descriptions number name pin type voltage range description 11, 12 gnd ground ground ground 1 30 hvout1 open drain output 2 0v to 10v open-drain output 1 fet gate driver 0v to 9v high-voltage fet gate driver 1 31 hvout2 open drain output 2 0v to 10v open-drain output 2 fet gate driver 0v to 9v high-voltage fet gate driver 2 27 in_out3 digital input 9 0v to 5.5v pld input 3 open drain output 2 open drain output 3 26 in_out4 digital input 9 0v to 5.5v pld input 4 open drain output 2 open drain output 4 23 in_out5 digital input 9 0v to 5.5v pld input 5 open drain output 2 open drain output 5 22 in_out6 digital input 9 0v to 5.5v pld input 6 open drain output 2 open drain output 6 20 in_out7 digital input 9 0v to 5.5v pld input 7 open drain output 2 open drain output 7 29 in1_pwrdn digital input 0v to 5.5v 3 pld logic input 1. 4, 5 when not used, this pin should be pulled down with a 10k resistor. v mo n 1 v mo n 2 v mo n 3 v mo n 4 v mo n 5 v mo n 6 i n 1_p w rd n i n 2 v cc h v out1 h v out2 i n _out3 i n _out4 i n _out5 i n _out6 i n _out7 tms tck tdi tdo v ccj g n d pld 16 macrocells 2 8 inp u ts jtag interface 6 analog v oltage monitor inp u ts po w er do w n logic 4 timers ISPPAC-POWR607 www.datasheet.co.kr datasheet pdf - http://www..net/
lattice semiconductor ISPPAC-POWR607 data sheet 4-3 28 in2 digital input 0v to 5.5v 3 pld logic input 2. when not used, this pin should be tied to gnd. 15 tck digital input 0v to 5.5v jtag test clock input 18 tdi digital input 0v to 5.5v jtag test data in - internal pull-up 14 tdo digital output 0v to 5.5v jtag test data out 19 tms digital input 0v to 5.5v jtag test mode select - internal pull-up 4, 21 vcc power 2.64v to 3.96v power supply 6 13 vccj power 2.25v to 3.6v vcc for jtag logic interface pins 7 2 vmon1 analog input -0.3v to 5.9v 8 voltage monitor input 1 3 vmon2 analog input -0.3v to 5.9v 8 voltage monitor input 2 5 vmon3 analog input -0.3v to 5.9v 8 voltage monitor input 3 6 vmon4 analog input -0.3v to 5.9v 8 voltage monitor input 4 7 vmon5 analog input -0.3v to 5.9v 8 voltage monitor input 5 10 vmon6 analog input -0.3v to 5.9v 8 voltage monitor input 6 1, 8, 9, 16, 17, 24, 25, 32 nc no connection not applicable no internal connection die pad nc no connection not applicable no internal connection 1. gnd pins must be connected together on the circuit board. 2. open-drain outputs require an external pull-up resistor to a supply. 3. in1_pwrdn and in2 are inputs to the pld. the thresholds for these pins are referenced by the voltage on vcc. 4. the power-down function is e 2 cmos programmable and when enabled is input level sensitive (enter power-down mode = low; exit power- down mode = high). 5. source of the power-down initiation can be assigned to either the in1_pwrdn pin or to an internally generated pld output signal called pld_pwrdn. when generated internally by the pld, the in1_pwrdn pin is only used to exit power-down mode (in1_pwrdn pin = high). 6. vcc pins must be connected together on the circuit board. 7. in power-down mode, vccj is internally pulled to gnd to turn off the jtag i/o pins. it is important, therefore, that the vcc j pin be open whenever power-down mode is initiated. if connected to a power supply during power-down mode, vccj will draw approximately 2.2m a. 8. the vmon inputs can be biased independently from vcc. unused vmon inputs should be tied to gnd. 9. thresholds of in_out3...in_out7 in the input mode are referenced by the voltage on vcc. pin descriptions (cont.) number name pin type voltage range description www.datasheet.co.kr datasheet pdf - http://www..net/
lattice semiconductor ISPPAC-POWR607 data sheet 4-4 absolute maximum ratings absolute maximum ratings are shown in the table below. stresses beyond those listed may cause permanent dam- age to the device. functional operation of the device at these or any other conditions beyond those indicated in the recommended operating conditions of this speci?ation is not implied. recommended operating conditions analog speci?ations symbol parameter conditions min. max. units v cc core supply -0.5 4.5 v v ccj jtag logic supply -0.5 6 v v in digital input voltage (all digital i/o pins) -0.5 6 v v mon v mon input voltage -0.5 6 v v tri voltage applied to tri-stated pins hvout[1:2] -0.5 11 v in_out[3:7] -0.5 6 v t s storage temperature -65 150 o c t a ambient temperature -65 125 o c i sinkmax maximum sink current on any output 23 ma symbol parameter conditions min. max. units v cc core supply voltage at pin 2.64 3.96 v v ccj jtag logic supply voltage at pin 2.25 3.6 v v in input voltage at digital input pins -0.3 5.5 v v mon input voltage at v mon pins -0.3 5.9 v v out open-drain output voltage in_out[3:7] pins -0.3 5.5 v hvout[1:2] pins in open- drain mode -0.3 10.4 v t aprog ambient temperature during programming (note 1) -40 85 o c t a ambient temperature power applied 1 -40 85 o c 1. the die pad on the bottom of the qfn/qfns package does not need to be electrically or thermally connected to ground. symbol parameter conditions min. typ. max. units i cc 1 supply current 3.5 5 ma i ccj 2 supply current 1ma i cc_pwrdn 3 power-down mode supply current icc + pin leakage currents 2 10 ? 1. includes currents on both v cc pins. 2. in power-down mode, vccj is internally pulled to gnd to turn off the jtag i/o pins. it is important, therefore, that the vccj pin be open whenever power-down mode is initiated. if connected to a power supply during power-down mode, vccj will draw approximately 2.2m a. 3. leakage measured in power-down mode with applied pin voltages as follows: vcc = 3.96v; in1_pwrdn , gnd = 0v; in2, vmonx and in_outx = 5.5v; hvoutx con?ured as fet drivers (hvoutx con?ured as open drain outputs have minor leakage path to ground and are not counted in total); vccj, tdi, tdo, tms and tck = open. www.datasheet.co.kr datasheet pdf - http://www..net/
lattice semiconductor ISPPAC-POWR607 data sheet 4-5 voltage monitors high voltage fet drivers power-on reset (internal) symbol parameter conditions min. typ. max. units r in input resistance 55 65 75 k c in input capacitance 8 pf v mon range programmable trip-point range 0.075 5.811 v v z sense near-ground sense threshold 70 75 80 mv v mon accuracy absolute accuracy of any trip-point 1 ?.5 1.5 % hyst hysteresis of any trip-point (relative to setting) 1% 1. guaranteed by characterization across v cc range, operating temperature, process. symbol parameter conditions min. typ. max. units v pp gate driver output voltage 8.1 9 9.9 v i outsrc gate driver source current (high state) controlled ramp setting 15 ? i outsink gate driver sink current (low state) fet turn off mode 1.0 2.5 ma symbol parameter conditions min. typ. max. units t rst delay from v th to start-up state 100 ? t start duration of start-up state 300 ? t bro minimum duration brown out required to enter reset state 15s t por delay from brown out to reset state 7 s v tl threshold below which por is low 1 2.2 v v th threshold above which por is high 1 2.5 v v t threshold above which por is valid 1 0.8 v 1. corresponds to vcc supply voltage. www.datasheet.co.kr datasheet pdf - http://www..net/
lattice semiconductor ISPPAC-POWR607 data sheet 4-6 figure 4-2. internal power-on reset v cc v t v tl v th por (internal) v mo n s ready (internal) t start pldclk (internal) reset state analog cali b ration t rst t bro start up state t por www.datasheet.co.kr datasheet pdf - http://www..net/
lattice semiconductor ISPPAC-POWR607 data sheet 4-7 ac/transient characteristics over recommended operating conditions figure 4-3. power-down mode timing symbol parameter conditions min. typ. max. units voltage monitors t pd12 propagation delay input to output glitch ?ter off 12 ? t pd48 propagation delay input to output glitch ?ter on 48 ? oscillators f pldclk pldclk frequency 240 250 260 khz timers timeout range range of programmable timers (128 steps) 0.032 1966 ms resolution spacing between available adjacent timer intervals 13 % accuracy timer accuracy -6.67 -12.5 % power-down mode t pwrdn time to enter power-down mode device previously on 100 ? t pwrdn_hold minimum required time in power- down mode before power-up can occur 100 ? t pwrup time to exit power-down mode 300 ? t pwrdn_up total time to enter and then exit power-down mode 500 ? i n 1_p w rd n (lo w = po w er-do w n) v cc icc t p w rd n t p w rup t p w rd n _up i cc_p w rd n i cc (nominal) t p w rd n _hold www.datasheet.co.kr datasheet pdf - http://www..net/
lattice semiconductor ISPPAC-POWR607 data sheet 4-8 digital speci?ations over recommended operating conditions symbol parameter conditions min. typ. max. units i il ,i ih input leakage, no pull-up/pull-down +/-10 ? i oh-hvout output leakage current hvout[1:2] in open drain mode and pulled up to 10v 35 60 ? i pu input pull-up current (tms, tdi) 70 ? v il voltage input, logic low 1 tdi, tms, tck, in[1:2], in_out[3:7] 2 , v ccj = 3.3v supply 0.8 v tdi, tms, tck, v ccj = 2.5v supply 0.7 v ih voltage input, logic high 1 tdi, tms, tck, in[1:2], in_out[3:7] 2 , v ccj = 3.3v supply 2.0 v tdi, tms, tck, v ccj = 2.5v supply 1.7 v ol hvout[1:2] (open drain mode), i sink = 10ma 0.8 v in_out[3:7] 3 i sink = 20ma 0.8 tdo i sink = 4ma 0.4 v oh tdo i src = 4ma v cc - 0.4 v i sinktotal 4 all digital outputs 67 ma 1. in_out[3:7], in[1:2] referenced to v cc ; tdo, tdi, tms, and tck referenced to v ccj . 2. when con?ured as inputs. 3. when con?ured as open drain outputs. 4. sum of maximum current sink from all digital outputs combined. reliable operation is not guaranteed if this value is exceeded . www.datasheet.co.kr datasheet pdf - http://www..net/
lattice semiconductor ISPPAC-POWR607 data sheet 4-9 timing for jtag operations figure 4-4. erase (user erase or erase all) timing diagram figure 4-5. programming timing diagram symbol parameter conditions min. typ. max. units t ispen program enable delay time 10 ? t ispdis program disable delay time 30 ? t hvdis high voltage discharge time, program 30 s t hvdis high voltage discharge time, erase 200 ? t cen falling edge of tck to tdo active 10 ns t cdis falling edge of tck to tdo disable 10 ns t su1 setup time 5 ns t h hold time 10 ns t ckh tck clock pulse width, high 20 ns t ckl tck clock pulse width, low 20 ns f max maximum tck clock frequency 25 mhz t co falling edge of tck to valid output 10 ns t pwv verify pulse width 30 ? t pwp programming pulse width 20 ms vih vil vih vil update-ir run-test/idle (erase) select-dr scan clock to shift-ir state and shift in the discharge instruction, then clock to the run-test/idle state run-test/idle (discharge) specified by the data sheet tms tck state t h t h t h t h t h t h t su1 t su1 t su1 t su1 t su1 t su1 t su2 t ckh t ckh t ckh t ckh t ckh t gkl t gkl tms tck state vih vil vih vi l update-ir run-test/idle (program) select-dr scan clock to shift-ir state and shift in the next instruction, which will stop the discharge process update-ir t su1 t su1 t su1 t su1 t su1 t h t h t h t h t h t ckl t pwp t ckh t ckh t ckh t ckh t ckl www.datasheet.co.kr datasheet pdf - http://www..net/
lattice semiconductor ISPPAC-POWR607 data sheet 4-10 figure 4-6. verify timing diagram figure 4-7. discharge timing diagram theory of operation analog monitor inputs the ISPPAC-POWR607 provides six independently programmable voltage monitor input circuits as shown in figure 4-8. one programmable trip-point comparator is connected to each analog monitoring input. each compara- tor reference has 192 programmable trip points over the range of 0.667v to 5.811v. additionally, a 75mv ?ero- detect threshold is selectable which allows the voltage monitors to determine if a monitored signal has dropped to ground level. this feature is especially useful for determining if a power supplys output has decayed to a substan- tially inactive condition after it has been switched off. figure 4-8. ISPPAC-POWR607 voltage monitors figure 4-8 shows the functional block diagram of one of the six voltage monitor inputs - ? (where x = 1...6). each voltage monitor can be divided into two sections: analog input, and filtering. the voltage input is monitored by a programmable trip-point comparator. table 4-1 and table 4-2 show all trip points and ranges to which any comparators threshold can be set. tms tck state vih vil vih vil update-ir run-test/idle (program) select-dr scan clock to shift-ir state and shift in the next instruction update-ir t h t h t h t h t h t ckh t ckh t ckh t ckl t pwv t ckh t ckl t su1 t su1 t su1 t su1 t su1 tms tck state vih vil vih vil update-ir run-test/idle (erase or program) select-dr scan clock to shift-ir state and shift in the verify instruction, then clock to the run-test/idle state run-test/idle (verify) specified by the data sheet actual t h t h t h t h t h t h t su1 t ckh t hvdis (actual) t ckh t ckh t ckh t ckl t pwp t pwv t ckh t ckl t pwv t su1 t su1 t su1 t su1 t su1 ISPPAC-POWR607 logic signal analog inp u t v mo n x trip point glitch filter pld array www.datasheet.co.kr datasheet pdf - http://www..net/
lattice semiconductor ISPPAC-POWR607 data sheet 4-11 each comparator outputs a high signal to the pld array if the voltage at its positive terminal (vmonx pin) is greater than its programmed trip point setting, otherwise it outputs a low signal. a hysteresis of approximately 1% of the setpoint is provided by the comparators to reduce false triggering as a result of input noise. the hysteresis provided by the voltage monitor is a function of the input divider setting. table 4-3 lists the typical hysteresis versus voltage monitor trip-point. programmable over-voltage and under-voltage thresholds figure 4-9 (a) shows the power supply ramp-up and ramp-down voltage waveforms. because of hysteresis, the comparator outputs change state at different thresholds depending on the direction of excursion of the monitored power supply. figure 4-9. (a) power supply voltage ramp-up and ramp-down waveform and the resulting comparator output, (b) corresponding to upper and lower trip points during power supply ramp-up the comparator output changes from logic 0 to 1 when the power supply voltage crosses the upper trip point (utp). during ramp down the comparator output changes from logic state 1 to 0 when the power supply voltage crosses the lower trip point (ltp). to monitor for over voltage fault conditions, the utp should be used. to monitor under-voltage fault conditions, the ltp should be used. tables 1 and 2 show both the under-voltage and over-voltage trip points, which are automatically selected in soft- ware depending on whether the user is monitoring for an over-voltage condition or an under-voltage condition. utp ltp monitored po w er s u pply v otlage comparator logic o u tp u t (a) ( b ) www.datasheet.co.kr datasheet pdf - http://www..net/
lattice semiconductor ISPPAC-POWR607 data sheet 4-12 table 4-1. trip point table used for over-voltage detection (in volts) table 4-2. trip point table used for under-voltage detection (in volts) ref/ monfedcba987654 1f 0.798 0.950 1.131 1.347 1.596 1.904 2.268 2.693 3.192 3.803 4.878 5.811 1e 0.790 0.941 1.120 1.333 1.580 1.885 2.245 2.666 3.159 3.764 4.829 5.751 1d 0.782 0.931 1.109 1.319 1.564 1.866 2.222 2.638 3.126 3.725 4.779 5.692 1c 0.774 0.921 1.097 1.306 1.547 1.847 2.198 2.611 3.095 3.686 4.729 5.632 1b 0.766 0.911 1.086 1.292 1.531 1.827 2.175 2.584 3.062 3.647 4.679 5.573 1a 0.757 0.902 1.074 1.278 1.515 1.808 2.152 2.556 3.029 3.609 4.629 5.514 19 0.749 0.892 1.063 1.264 1.498 1.788 2.129 2.529 2.997 3.570 4.580 5.454 18 0.741 0.882 1.051 1.250 1.482 1.769 2.106 2.501 2.964 3.531 4.530 5.395 17 0.733 0.872 1.039 1.237 1.466 1.749 2.083 2.473 2.931 3.492 4.480 5.336 16 0.725 0.864 1.028 1.223 1.449 1.730 2.060 2.446 2.899 3.453 4.430 5.277 15 0.716 0.854 1.016 1.209 1.433 1.710 2.037 2.418 2.866 3.414 4.380 5.217 14 0.708 0.844 1.005 1.195 1.417 1.691 2.014 2.391 2.834 3.375 4.331 5.158 13 0.700 0.835 0.993 1.181 1.400 1.671 1.990 2.364 2.801 3.337 4.281 5.099 12 0.692 0.825 0.981 1.168 1.384 1.652 1.967 2.336 2.769 3.298 4.231 5.040 11 0.684 0.815 0.970 1.154 1.369 1.632 1.944 2.309 2.736 3.259 4.181 4.980 10 0.676 0.805 0.958 1.140 1.352 1.614 1.921 2.281 2.703 3.220 4.131 4.921 low v 75 mv ref/ monfedcba987654 1f 0.790 0.941 1.120 1.333 1.580 1.885 2.245 2.666 3.159 3.764 4.829 5.751 1e 0.782 0.931 1.109 1.319 1.564 1.866 2.222 2.638 3.126 3.725 4.779 5.692 1d 0.774 0.921 1.097 1.306 1.547 1.847 2.198 2.611 3.095 3.686 4.729 5.632 1c 0.766 0.911 1.086 1.292 1.531 1.827 2.175 2.584 3.062 3.647 4.679 5.573 1b 0.757 0.902 1.074 1.278 1.515 1.808 2.152 2.556 3.029 3.609 4.629 5.514 1a 0.749 0.892 1.063 1.264 1.498 1.788 2.129 2.529 2.997 3.570 4.580 5.454 19 0.741 0.882 1.051 1.250 1.482 1.769 2.106 2.501 2.964 3.531 4.530 5.395 18 0.733 0.872 1.039 1.237 1.466 1.749 2.083 2.473 2.931 3.492 4.480 5.336 17 0.725 0.864 1.028 1.223 1.449 1.730 2.060 2.446 2.899 3.453 4.430 5.277 16 0.716 0.854 1.016 1.209 1.433 1.710 2.037 2.418 2.866 3.414 4.380 5.217 15 0.708 0.844 1.005 1.195 1.417 1.691 2.014 2.391 2.834 3.375 4.331 5.158 14 0.700 0.835 0.993 1.181 1.400 1.671 1.990 2.364 2.801 3.337 4.281 5.099 13 0.692 0.825 0.981 1.168 1.384 1.652 1.967 2.336 2.769 3.298 4.231 5.040 12 0.684 0.815 0.970 1.154 1.369 1.632 1.944 2.309 2.736 3.259 4.181 4.980 11 0.676 0.805 0.958 1.140 1.352 1.614 1.921 2.281 2.703 3.220 4.131 4.921 10 0.667 0.796 0.947 1.126 1.336 1.594 1.897 2.254 2.671 3.181 4.082 4.861 low v 75 mv www.datasheet.co.kr datasheet pdf - http://www..net/
lattice semiconductor ISPPAC-POWR607 data sheet 4-13 table 4-3. comparator hysteresis vs. trip-point the second section in the ISPPAC-POWR607s input voltage monitor is a digital ?ter. when enabled, the compara- tor output will be delayed by a ?ter time constant of 48?, and is especially useful for reducing the possibility of false triggering from noise that may be present on the voltages being monitored. when the ?ter is disabled, the comparator output will be delayed by 12?. in both cases, enabled or disabled, the ?ters also provide synchroniza- tion of the input signals to the pld clock. this synchronous sampling feature effectively eliminates the possibility of race conditions from occurring in any subsequent logic that is implemented in the ISPPAC-POWR607s internal pld logic. pld block figure 4-10 shows the ISPPAC-POWR607 pld architecture, which is derived from lattice's ispmach 4000 cpld. the pld architecture allows ?xibility in designing various state machines and control functions for power supply management. the and array has 28 inputs and generates 81 product terms. the product terms are fed into a single logic block made up of 16 macrocells. the output signals of the ISPPAC-POWR607 device are derived from the pld as shown in figure 4-10. trip-point range (v) hysteresis (mv) low limit high limit 0.667 0.798 8 0.796 0.950 10 0.947 1.131 12 1.126 1.347 14 1.336 1.596 17 1.594 1.904 19 1.897 2.268 23 2.254 2.693 28 2.671 3.192 33 3.181 3.803 39 4.082 4.878 50 4.861 5.811 60 75 mv 0 (disabled) www.datasheet.co.kr datasheet pdf - http://www..net/
lattice semiconductor ISPPAC-POWR607 data sheet 4-14 figure 4-10. ISPPAC-POWR607 pld architecture macrocell architecture the macrocell shown in figure 4-11 is the heart of the pld. the basic macrocell has ?e product terms that feed the or gate and the ?p-?p. the ?p-?p in each macrocell is independently con?ured. it can be programmed to function as a d-type or t-type ?p-?p. combinatorial functions are realized by bypassing the ?p-?p. the polarity control and xor gates provide additional ?xibility for logic synthesis. the ?p-?ps clock is driven from the com- mon pld clock that is generated by dividing the 8 mhz master clock (mclk) by 32. the macrocell also supports asynchronous reset and preset functions, derived from either product terms or the power-on reset signal. the resources within the macrocells share routing and contain a product term allocation array. the product term alloca- tion array greatly expands the plds ability to implement complex logical functions by allowing logic to be shared between adjacent blocks and distributing the product terms to allow for wider decode functions. all the digital inputs are registered by mclk and all vmon comparator outputs are registered using the pld clock to synchronize them to the pld logic as shown in figure 4-10. reset o u tp u t feed b ack v mo n [1:6] i n _out[3:7] 6 5 timer1 timer0 timer2 timer3 i r p timer clock 16 pld clock mclk 4 16 16 h v out[1:2] i n 2 a n d array 2 8 inp u ts inp u t register inp u t register 8 1 p-terms sleep/ w ake logic i n 1_p w rd n v cc glb generic logic block 16 macrocell 8 1 p-terms 8 1 pld_p w rd n i n _out[3:7] www.datasheet.co.kr datasheet pdf - http://www..net/
lattice semiconductor ISPPAC-POWR607 data sheet 4-15 figure 4-11. ISPPAC-POWR607 macrocell block diagram clock and timer functions figure 4-12 shows a block diagram of the ISPPAC-POWR607s internal clock and timer systems. the master clock operates at a ?ed frequency of 8mhz, from which a ?ed 250khz pld clock is derived. figure 4-12. clock and timer system the internal oscillator runs at a ?ed frequency of 8 mhz. this signal is used as a source for the pld and timer clocks. it is also used for clocking the comparator outputs and clocking the digital ?ters in the voltage monitor cir- cuits. a divide-by-32 prescaler divides the internal 8mhz oscillator down to 250khz for the pld clock and for the pro- grammable timers. each of the four timers provides independent timeout intervals ranging from 32? to 1.96 sec- onds in 128 steps. pt0 pt1 pt2 pt3 pt4 d/t q r p to pld output clk clock polarity macrocell flip-flop provides d, t, or combinatorial output with polarity product term allocation power on reset global polarity fuse for init product term block init product term internal oscillator 8 mhz 32 timer 0 timer 1 timer 3 timer 2 pld c lock to/from pld www.datasheet.co.kr datasheet pdf - http://www..net/
lattice semiconductor ISPPAC-POWR607 data sheet 4-16 digital inputs and optional device power down the ISPPAC-POWR607 has two dedicated digital input pins which are registered by mclk as shown in figure 4-10 and then connect to the input and array of the pld (in[1:2]). the pins are standard cmos inputs and are refer- enced to vcc. the optional power-down mode is a programmable feature controlled via the in1_pwrdn pin. it is used to power- down the ISPPAC-POWR607 and power it up again as desired. when in power-down mode, the ISPPAC-POWR607 draws a minimal amount of supply current (less than 10? max). the device is brought out of power-down mode by applying a logic high signal on the level sensitive in1_pwrdn pin. when it exits power-down mode, the ISPPAC-POWR607 is internally reset to its initial power-on state before resum- ing normal operation. the logic and limited memory needed to ?akeup on cue are all that remain on during power-down mode. other functions and capabilities, such as voltage monitoring, fet drive capability and pld logic states are all lost when the ISPPAC-POWR607 is in power-down mode. open drain outputs and mosfet driver pins go into hi-z mode and all digital inputs, except in1_pwrdn , stop responding to logic input signals. there are two e 2 cmos bits associated with the ISPPAC-POWR607 power-down function. con?uring these bits for speci? power-down functionality is achieved using pac-designer, a software design tool for lattice programmable mixed signal devices. table 4-4 is a truth table detailing the operation of the ISPPAC-POWR607 power-down logical control function. table 4-4. pwrdn truth table to use the ISPPAC-POWR607's power-down function, the e 2 cmos pwrdn enable bit must be set during initial device design con?uration. power-down is disabled otherwise (the initial default). when power is ?st applied to ISPPAC-POWR607, the device checks to see if a power-down condition exists, and then if it is already present will proceed immediately to the power-down state. during the brief period that the device is on, it will consume full power but it will proceed directly to power-down mode without executing any state machine instructions, etc. this time to initially detect the power-down command and then shut down is given in the power-down speci?ations section of the datasheet. in addition to the in1_pwrdn pin, table 4-4 shows how an alternate signal from the pld called pld_pwrdn can be used to initiate power-down (not the default). this can be useful when power-down is the last step in a series of ISPPAC-POWR607 pld controlled states, such as turning off supplies in sequence or acknowledging pro- cessor signals, etc. note : the only way to exit power-down mode, regardless of how it's initiated, is with the in1_pwrdn pin. applying a logic high to in1_pwrdn will always return the ISPPAC-POWR607 to normal operation. finally, whenever the ISPPAC-POWR607 is in power-down mode, vccj is internally pulled to gnd to turn off the jtag i/o pins. it is important, therefore, that the vccj pin be open when power-down mode is initiated. if connected to a power supply during power-down mode, vccj will draw approximately 2.2ma. dual purpose digital i/o pins the ISPPAC-POWR607 provides seven possible digital outputs, hvout[1:2] and in_out[3:7]. any number of these pins can be con?ured to act as open drain outputs, providing a high degree of ?xibility when interfacing to in1_ p p p p w w w w r r r r d d d d n n n n input pin pld_pwrdn internal signal pwrdn enable bit pwrdn source bit power mode x x clear x normal 1 x set x normal 0 x set in1_ pwrdn pin power-down 0 0 set internal signal pld_pwrdn power-down note: when in power-down mode, the ISPPAC-POWR607 will not respond to logic inputs (except to the in1_ pwrdn pin) and all outputs will be high impedance. www.datasheet.co.kr datasheet pdf - http://www..net/
lattice semiconductor ISPPAC-POWR607 data sheet 4-17 logic signals, leds, opto-couplers, and power supply control inputs. the hvout[1:2] pins can also be con?ured as high voltage fet drivers and are discussed more in the next section. the digital i/o pins can also be pro- grammed to be true digital inputs. it should be noted the in_out[3:7] pins are not true bidirectional pins and individually they can only act as an input or as an output, but not both at the same time. a simpli?d diagram of how this is accomplished is shown in figure 4-13. there is a user con?urable e 2 cmos bit for each of the in_out[3:7] pins that determines whether the pin is a dedicated input or open drain output. figure 4-13. programmable digital input/output pins (in_out) the architecture takes advantage of routing that normally feeds all pld macrocell outputs back into the input and array. output pins are realized when some number of macrocell outputs are selected from the pld to become dig- ital open drain outputs. when programmed to be outputs, in_outx pins are con?ured exactly this way. when pro- grammed to be digital input pins, the open drain buffer is permanently turned off (set to hi-z) and the input from in_outx pin goes to the input array instead of the macrocells output. the macrocell output is still available and can be connected to a different output pin if desired. when the in-outx pins are con?ured as digital input pins, the signal is registered by mclk prior to going to the input and array the same as the in1 and in2 digital inputs. high-voltage outputs the ISPPAC-POWR607s hvout1-hvout2 output pins can be programmed to operate either as high-voltage fet drivers or optionally as open drain digital outputs. figure 4-14 shows the details of the hvout gate drivers. each of these outputs is controlled from the pld. figure 4-14. basic function diagram for an output in high voltage mosfet gate driver mode figure 4-14 shows the hvout functionality when programmed as a fet driver. in this mode the output either sources current from a charge pump or sinks current. the voltage that the output level at the pin will rise to is typi- cally 9v. (this level is not programmable, unlike other power manager ii devices). the maximum voltage levels required depend on the gate-to-source threshold of the fet being driven and the power supply voltage being switched. the maximum voltage level needs to be suf?ient to bias on the gate-to-source threshold and also from macrocell o u tp u ts 1 0 open drain o u tp u t b u ffer inp u t b u ffer to pld inp u t array i n _outx inp u t / feed b ack m u x o u tp u t ro u ting i/o config (e 2 cmos) i source (15 a) i si n k 2.5ma (1ma, min.) charge p u mp (9 v ) inp u t s u pply load h v outx pin digital control from pld + - www.datasheet.co.kr datasheet pdf - http://www..net/
lattice semiconductor ISPPAC-POWR607 data sheet 4-18 accommodate the load voltage at the fets source, when the source pin of the fet is tied to the supply of the tar- get board. when the hvout pin is sourcing current (charging a fet gate) the source current is 15?. when the driver is turned to the off state, the driver will sink current to ground, and this sink current is typically 2.5ma (1ma min.) to quickly turn off the fet. during initial power up and for short periods of time during programming, the hvoutx pins will assume a high impedance output con?uration (hi-z). this occurs whether the pin is con?ured as a high voltage mosfet driver or as an open drain output. it happens due to the period of uncertainty before the e 2 cmos memory is resolved at initial turn on and whenever being re-programmed. to insure any fets controlled by ISPPAC-POWR607 hvoutx pins are always off during these times, place a 10m (min) resistor between each hvoutx pin and ground. since this will subtract less than 1ua from the total drive capability of the hvout pin in fet driver mode, it will have a negligible affect on its speci?d drive performance. software-based design environment designers can con?ure the ISPPAC-POWR607 using pac-designer, an easy to use, microsoft windows compati- ble program. circuit designs are entered graphically and then veri?d, all within the pac-designer environment. full device programming is supported using pc parallel port i/o operations and a download cable connected to the serial programming interface pins of the ISPPAC-POWR607. a library of con?urations is included with basic solu- tions and examples of advanced circuit techniques are available on the lattice web site for downloading. in addi- tion, comprehensive on-line and printed documentation is provided that covers all aspects of pac-designer operation. the pac-designer schematic window, shown in figure 4-15, provides access to all con?urable isppac- powr607 elements via its graphical user interface. all analog input and output pins are represented. static or non- con?urable pins such as power, ground, and the serial digital interface are omitted for clarity. any element in the schematic window can be accessed via mouse operations as well as menu commands. when completed, con?u- rations can be saved, simulated, and downloaded to devices. figure 4-15. pac-designer ISPPAC-POWR607 design entry screen www.datasheet.co.kr datasheet pdf - http://www..net/
lattice semiconductor ISPPAC-POWR607 data sheet 4-19 in-system programming the ISPPAC-POWR607 is an in-system programmable device. this is accomplished by integrating all e 2 con?ura- tion memory on-chip. programming is performed through a 4-wire, ieee 1149.1 compliant serial jtag interface at normal logic levels. once a device is programmed, all con?uration information is stored on-chip, in non-volatile e 2 cmos memory cells. the speci?s of the ieee 1149.1 serial interface and all ISPPAC-POWR607 instructions are described in the jtag interface section of this data sheet. user electronic signature a user electronic signature (ues) feature is included in the e 2 cmos memory of the ISPPAC-POWR607. this con- sists of 32 bits that can be con?ured by the user to store unique data such as id codes, revision numbers or inven- tory control data. the speci?s of this feature are discussed in the ieee 1149.1 serial interface section of this data sheet. electronic security an electronic security ?use (esf) bit is provided in every ISPPAC-POWR607 device to prevent unauthorized read- out of the e 2 cmos con?uration bit patterns. once programmed, this cell prevents further access to the functional user bits in the device. this cell can only be erased by reprogramming the device, so the original con?uration can- not be examined once programmed. usage of this feature is optional. the speci?s of this feature are discussed in the ieee 1149.1 serial interface section of this data sheet. production programming support once a ?al con?uration is determined, an ascii format jedec ?e can be created using the pac-designer soft- ware. devices can then be ordered through the usual supply channels with the users speci? con?uration already preloaded into the devices. by virtue of its standard interface, compatibility is maintained with existing production programming equipment, giving customers a wide degree of freedom and ?xibility in production planning. evaluation fixture because the features of an ISPPAC-POWR607 are all included in the larger isppac-powr1220at8 device, designs implemented in an ISPPAC-POWR607 can be veri?d using an isppac-powr1220at8 engineering proto- type board connected to the parallel port of a pc with a lattice ispdownload cable. the board demonstrates proper layout techniques and can be used in real time to check circuit operation as part of the design process. input and output connections are provided to aid in the evaluation of the functionality implemented in isppac- powr607 for a given application. (figure 4-16). figure 4-16. download from a pc ieee standard 1149.1 interface (jtag) serial port programming interface communication with the ISPPAC-POWR607 is facilitated via an ieee 1149.1 test access port (tap). it is used by the ISPPAC-POWR607 as a serial programming interface. a brief description of the ispdownload cable (6') 4 other system circuitry isppac-powr 1220at8 device pac-designer software www.datasheet.co.kr datasheet pdf - http://www..net/
lattice semiconductor ISPPAC-POWR607 data sheet 4-20 ISPPAC-POWR607 jtag interface follows. for complete details of the reference speci?ation, refer to the publica- tion, standard test access port and boundary-scan architecture, ieee std 1149.1-1990 (which now includes ieee std 1149.1a-1993). overview an ieee 1149.1 test access port (tap) provides the control interface for serially accessing the digital i/o of the isp- pac-powr607. the tap controller is a state machine driven with mode and clock inputs. given in the correct sequence, instructions are shifted into an instruction register, which then determines subsequent data input, data output, and related operations. device programming is performed by addressing the con?uration register, shifting data in, and then executing a program con?uration instruction, after which the data is transferred to internal e 2 cmos cells. it is these non-volatile cells that store the con?uration or the ISPPAC-POWR607. a set of instruc- tions are de?ed that access all data registers and perform other internal control operations. for compatibility between compliant devices, two data registers are mandated by the ieee 1149.1 speci?ation. others are func- tionally speci?d, but inclusion is strictly optional. finally, there are provisions for optional data registers de?ed by the manufacturer. the two required registers are the bypass and boundary-scan registers. figure 4-17 shows how the instruction and various data registers are organized in an ISPPAC-POWR607. figure 4-17. ISPPAC-POWR607 tap registers tap controller speci?s the tap is controlled by the test clock (tck) and test mode select (tms) inputs. these inputs determine whether an instruction register or data register operation is performed. driven by the tck input, the tap consists of a small 16-state controller design. in a given state, the controller responds according to the level on the tms input as shown in figure 4-18. test data in (tdi) and tms are latched on the rising edge of tck, with test data out (tdo) becoming valid on the falling edge of tck. there are six steady states within the controller: test-logic-reset, run- test/idle, shift-data-register, pause-data-register, shift-instruction-register and pause-instruction-register. but there is only one steady state for the condition when tms is set high: the test-logic-reset state. this allows a reset of the test logic within ?e tcks or less by keeping the tms input high. test-logic-reset is the power-on default state. address register (61 bits) e 2 cmos non-volatile memory ues register (32 bits) idcode register (32 bits) bypass register (1 bit) instruction register (8 bits) test access port (tap) logic output latch tdi tck tms tdo multiplexer data register (81 bits) www.datasheet.co.kr datasheet pdf - http://www..net/
lattice semiconductor ISPPAC-POWR607 data sheet 4-21 figure 4-18. tap states when the correct logic sequence is applied to the tms and tck inputs, the tap will exit the test-logic-reset state and move to the desired state. the next state after test-logic-reset is run-test/idle. until a data or instruction shift is performed, no action will occur in run-test/idle (steady state = idle). after run-test/idle, either a data or instruc- tion shift is performed. the states of the data and instruction register blocks are identical to each other differing only in their entry points. when either block is entered, the ?st action is a capture operation. for the data regis- ters, the capture-dr state is very simple: it captures (parallel loads) data onto the selected serial data path (previ- ously chosen with the appropriate instruction). for the instruction register, the capture-ir state will always load the idcode instruction. it will always enable the id register for readout if no other instruction is loaded prior to a shift-dr operation. this, in conjunction with mandated bit codes, allows a ?lind interrogation of any device in a compliant ieee 1149.1 serial chain. from the capture state, the tap transitions to either the shift or exit1 state. normally the shift state follows the capture state so that test data or status information can be shifted out or new data shifted in. following the shift state, the tap either returns to the run-test/idle state via the exit1 and update states or enters the pause state via exit1. the pause state is used to temporarily suspend the shifting of data through either the data or instruction register while an external operation is performed. from the pause state, shifting can resume by reentering the shift state via the exit2 state or be terminated by entering the run-test/idle state via the exit2 and update states. if the proper instruction is shifted in during a shift-ir operation, the next entry into run-test/idle initiates the test mode (steady state = test). this is when the device is actually programmed, erased or veri?d. all other instructions are executed in the update state. test instructions like data registers, the ieee 1149.1 standard also mandates the inclusion of certain instructions. it outlines the function of three required and six optional instructions. any additional instructions are left exclusively for the manu- facturer to determine. the instruction word length is not mandated other than to be a minimum of two bits, with only the bypass and extest instruction code patterns being speci?ally called out (all ones and all zeroes respec- tively). the ISPPAC-POWR607 contains the required minimum instruction set as well as one from the optional instruction set. in addition, there are several proprietary instructions that allow the device to be con?ured and ver- i?d. table 4-5 lists the instructions supported by the ISPPAC-POWR607 jtag test access port (tap) controller: test-logic-rst run-test/idle select-dr-scan select-ir-scan capture-dr capture-ir shift-dr shift-ir exit1-dr exit1-ir pause-dr pause-ir exit2-dr exit2-ir update-dr update-ir 1 0 00 00 00 11 00 00 11 11 00 11 00 11 11 11 1 0 note: the value shown adjacent to each state transition in this figure represents the signal present at tms at the time of a rising edge at tck. www.datasheet.co.kr datasheet pdf - http://www..net/
lattice semiconductor ISPPAC-POWR607 data sheet 4-22 table 4-5. ISPPAC-POWR607 tap instruction table bypass is one of the three required instructions. it selects the bypass register to be connected between tdi and tdo and allows serial data to be transferred through the device without affecting the operation of the isppac- powr607. the ieee 1149.1 standard de?es the bit code of this instruction to be all ones (11111111). the required sample/preload instruction dictates the boundary-scan register be connected between tdi and tdo. the ISPPAC-POWR607 has no boundary scan register, so for compatibility it defaults to the bypass mode whenever this instruction is received. the bit code for this instruction is de?ed by lattice as shown in table 4-5. the extest (external test) instruction is required and would normally place the device into an external boundary test mode while also enabling the boundary scan register to be connected between tdi and tdo. again, since the ISPPAC-POWR607 has no boundary scan logic, the device is put in the bypass mode to ensure speci?ation com- patibility. the bit code of this instruction is de?ed by the 1149.1 standard to be all zeros (00000000). the optional idcode (identi?ation code) instruction is incorporated in the ISPPAC-POWR607 and leaves it in its functional mode when executed. it selects the device identi?ation register to be connected between tdi and tdo. the identi?ation register is a 32-bit shift register containing information regarding the ic manufacturer, device type and version code (figure 4-19). access to the identi?ation register is immediately available, via a tap data scan operation, after power-up of the device, or by issuing a test-logic-reset instruction. the bit code for this instruction is de?ed by lattice as shown in table 4-5. instruction command code comments bulk_erase 0000 0011 bulk erase device bypass 1111 1111 bypass - connect tdo to tdi discharge 0001 0100 fast vpp discharge erase_done_bit 0010 0100 erases ?one bit only extest 0000 0000 bypass - connect tdo to tdi idcode 0001 0110 read contents of manufacturer id code (32 bits) outputs_highz 0001 1000 force all outputs to high-z state, including fet driver outputs sample/preload 00011100 sample/preload. default to bypass. program_disable 0001 1110 disable program mode program_done_bit 0010 1111 programs the done bit program_enable 0001 0101 enable program mode program_security 0000 1001 program security fuse reset 0010 0010 resets device pld_address_shift 0000 0001 pld_address register (61 bits) pld_data_shift 0000 0010 pld_data register (81 bits) pld_init_addr_for_prog_incr 0010 0001 initialize the address register for auto increment pld_prog_incr 0010 0111 program column register to e 2 and auto increment address register pld_program 0000 0111 program pld data register to e 2 pld_verify 0000 1010 veri?s pld column data pld_verify_incr 0010 1010 load column register from e 2 and auto increment address register ues_program 0001 1010 program ues bits into e 2 ues_read 0001 0111 read contents of ues register from e 2 (32 bits) www.datasheet.co.kr datasheet pdf - http://www..net/
lattice semiconductor ISPPAC-POWR607 data sheet 4-23 figure 4-19. ISPPAC-POWR607 id code ISPPAC-POWR607 speci? instructions there are 25 unique instructions speci?d by lattice for the ISPPAC-POWR607. these instructions are primarily used to interface to the various user registers and the e 2 cmos non-volatile memory. additional instructions are used to control or monitor other features of the device. a brief description of each unique instruction is provided in detail below, and the bit codes are found in table 4-5. pld_address_shift ?this instruction is used to set the address of the pld and/arch arrays for subsequent program or read operations. this instruction also forces the outputs into the outputs_highz. pld_data_shift ?this instruction is used to shift pld data into the register prior to programming or reading. this instruction also forces the outputs into the outputs_highz. pld_init_addr_for_prog_incr ?this instruction prepares the pld address register for subsequent pld_prog_incr or pld_verify_incr instructions. pld_prog_incr ?this instruction programs the pld data register for the current address and increments the address register for the next set of data. pld_program ?this instruction programs the selected pld and/arch array column. the speci? column is preselected by using pld_address_shift instruction. the programming occurs at the second rising edge of the tck in run-test-idle jtag state. the device must already be in programming mode (program_enable instruction). this instruction also forces the outputs into the outputs_highz. program_security ?this instruction is used to program the electronic security fuse (esf) bit. programming the esf bit protects proprietary designs from being read out. the programming occurs at the second rising edge of the tck in run-test-idle jtag state. the device must already be in programming mode (program_enable instruction). this instruction also forces the outputs into the outputs_highz. pld_verify ?this instruction is used to read the content of the selected pld and/arch array column. this speci? column is preselected by using pld_address_shift instruction. this instruction also forces the outputs into the outputs_highz. discharge ?this instruction is used to discharge the internal programming supply voltage after an erase or pro- gramming cycle and prepares ISPPAC-POWR607 for a read cycle. this instruction also forces the outputs into the outputs_highz. bulk_erase ?this instruction will bulk erase all e 2 cmos bits (cfg, pld, ues, and esf) in the isppac- powr607. the device must already be in programming mode (program_enable instruction). this instruction also forces the outputs into the outputs_highz. outputs_highz ?this instruction turns off all of the open-drain output transistors. pins that are programmed as fet drivers will be placed in the active low state. this instruction is effective after update-instruction-register jtag state. program_enable ?this instruction enables the programming mode of the ISPPAC-POWR607. this instruction also forces the outputs into the outputs_highz. 0000 0000 0001 0100 0111 / 0000 0100 001 / 1 (ISPPAC-POWR607) msb lsb part number (20 bits) 00147h = ISPPAC-POWR607 jedec manufacturer identity code for lattice semiconductor (11 bits) constant 1 (1 bit) per 1149.1-1990 www.datasheet.co.kr datasheet pdf - http://www..net/
lattice semiconductor ISPPAC-POWR607 data sheet 4-24 idcode ?this instruction connects the output of the identi?ation code data shift (idcode) register to tdo (figure 4-20), to support reading out the identi?ation code. figure 4-20. idcode register program_disable ?this instruction disables the programming mode of the ISPPAC-POWR607. the test- logic-reset jtag state can also be used to cancel the programming mode of the ISPPAC-POWR607. ues_read ?this instruction both reads the e 2 cmos bits into the ues register and places the ues register between the tdi and tdo pins (as shown in figure 4-17), to support programming or reading of the user electronic signature bits. figure 4-21. ues register ues_program ?this instruction will program the content of the ues register into the ues e 2 cmos memory. the device must already be in programming mode (program_enable instruction). this instruction also forces the outputs into the outputs_highz. erase_done_bit ?this instruction clears the ?one bit, which prevents the ISPPAC-POWR607 sequence from starting. program_done_bit ?this instruction sets the ?one bit, which enables the ISPPAC-POWR607 sequence to start. reset ?this instruction resets the pld sequence and output macrocells. the condition of the ISPPAC-POWR607 is the same as initial turn-on after por is completed. pld_verify_incr ?this instruction reads out the pld data register for the current address and increments the address register for the next read. notes: in all of the descriptions above, outputs_highz refers both to the instruction and the state of the digital and fet driver output pins, in which all are tri-stated. before any of the above programming instructions are executed, the respective e 2 cmos bits need to be erased using the corresponding erase instruction. tdo bit 0 bit 1 bit 2 bit 3 bit 4 bit 27 bit 28 bit 29 bit 30 bit 31 tdo bit 0 bit 1 bit 2 bit 3 bit 4 bit 11 bit 12 bit 13 bit 14 bit 15 www.datasheet.co.kr datasheet pdf - http://www..net/
lattice semiconductor ISPPAC-POWR607 data sheet 4-25 package diagrams 32-pin qfns dimensions in millimeters applies to exposed portion of terminals. dimensions and tolerances exact shape and size of this dimension b applies to plated terminal and is measured between 0.15 and 0.30 mm from terminal tip. notes: unless otherwise specified all dimensions are in millimeters. 5 2. 4 3 1. feature is optional. per ansi y14.5m. seating plane side view 0.15 c top view pin 1 id area 3 1 n d a 2x located in this area pin #1 id fiducial b bottom view e 0.15 2x b c e2 n 1 a c d2 b 0.10 4 a c m b e symbol a a1 a3 d d2 e e2 b e l nom. max. min. 0.00 1.25 0.18 0.90 0.02 2.70 0.24 1.00 0.05 3.75 0.30 0.30 0.40 0.50 0.80 0.2 ref 5.0 bsc 5.0 bsc 1.25 2.70 3.75 0.50 bsc 3 0.08 5 c a3 a1 a view a view a 0.50 typ 4x 32x l www.datasheet.co.kr datasheet pdf - http://www..net/
lattice semiconductor ISPPAC-POWR607 data sheet 4-26 32-pin qfn 1 dimensions in millimeters 1. use 32-pin qfns package for all new designs. refer to pcn #13a-08 for 32-pin qfn package discontinuance. 3.5 0.20 a c 2x seating plane 2x 0.20 b c pin 1 id 3 n 1 b a 5.00 0.25 2x c a b 0.25 2x cb a a1 a3 a2 l e 0.08 5 c e2 b 0.10 a m c n 1 d2 3 4 4x 32x c pin #1 id fiducial located in this area 5.00 3 4 5 4.75 4.75 0 0 top view bottom view side view all dimensions are in millimeters. notes: unless otherwise specified 2. 1. 1.00 1.00 0.50 0.05 max. per ansi y14.5m. 0.20 and 0.25 mm from terminal tip. terminal and is measured between dimension b applies to plated feature is optional. exact shape and size of this 0.20 ref e l d2 a3 a2 0.50 bsc 0.40 0.30 0.65 dimensions and tolerances - 0.00 min. symbol a1 a 0.85 0.01 nom. applies to exposed portion of terminals. 2.70 1.25 3.25 2.70 e2 1.25 3.25 12 - - 0.00 b 0.18 0.24 0.30 diepad (exposed backside) www.datasheet.co.kr datasheet pdf - http://www..net/
lattice semiconductor ISPPAC-POWR607 data sheet 4-27 part number description ISPPAC-POWR607 ordering information conventional packaging industrial lead-free packaging industrial part number package pins ISPPAC-POWR607-01s32i qfns 32 ISPPAC-POWR607-01n32i 1 qfn 32 1. use qfns package. qfn package devices have been discontinued via pcn #13a-08. part number package pins ISPPAC-POWR607-01sn32i lead-free qfns 32 ISPPAC-POWR607-01nn32i 1 lead-free qfn 32 1. use qfns package. qfn package devices have been discontinued via pcn #13a-08. device number ISPPAC-POWR607 - 01xx32x operating temperature range i = industrial (-40 o c to +85 o c) package s32 = 32-pin qfns 1 sn32 = lead-free 32-pin qfns n32 = 32-pin qfn 2 nn32 = lead-free 32-pin qfn 2 1. contact factory for package availability. 2. use 32-pin qfns package for all new designs. refer to pcn #13a-08 for 32-pin qfn package discontinuance. performance grade 01 = standard device family www.datasheet.co.kr datasheet pdf - http://www..net/
lattice semiconductor ISPPAC-POWR607 data sheet 4-28 package options technical support assistance hotline: 1-800-lattice (north america) +1-408-826-6002 (outside north america) e-mail: isppacs@latticesemi.com internet: www.latticesemi.com revision history date version change summary september 2006 01.0 initial release. april 2007 01.1 references to die pad added to pin descriptions table, recommended operating condi- tions table and package options diagram. august 2007 01.2 changes to hvout pin speci?ations. december 2007 01.3 final data sheet. june 2008 01.4 added timing diagram and timing parameters to "power-on reset" speci?ations. modi?d pld architecture ?ure to show input registers. december 2008 01.5 added 32-pin qfns package ordering part number information per pcn #13a-08. february 2009 01.6 updated ISPPAC-POWR607 pld architecture diagram to clarify that the digital inputs are registered inputs to the and array. updated digital inputs and optional device power down text section. updated dual purpose digital i/o pins text section. 24 23 22 21 20 19 1 8 17 1 2 3 4 5 6 7 8 nc vmon1 vmon2 die pad nc vcc vmon3 vmon4 nc vmon5 nc in_out5 in_out6 vcc in_out7 tms tdi nc nc vmon6 gnd gnd vccj tdo tck nc nc hvout2 hvout1 in1_pwrdn in2 in_out3 in_out4 nc 9 10111213141516 ISPPAC-POWR607 32-pin qfns 32 31 30 29 2 8 27 26 25 www.datasheet.co.kr datasheet pdf - http://www..net/

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